View AD640BPZ_9038738.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

atn out amplifier/limiter full-wave detector atn lo atn com sig +in sig Cin atn com com 27v 30v 270v atn in 1kv rg1 rg0 rg2 Cv s bl1 +v s log out log com sig +out sig Cout bl2 itc 20 1 intercept positioning bias 19 3 2 4 18 5 6 gain bias regulator amplifier/limiter full-wave detector amplifier/limiter full-wave detector 10db amplifier/limiter full-wave detector 10db 10db amplifier/limiter full-wave detector 17 16 14 13 1kv 7 11 10 9 8 12 slope bias regulator 15 10db 10db a dc-coupled demodulating 120 mhz logarithmic amplifier ad640 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999-2016 features complete, fully calibrated monolithic system five stages, each having 10 db gain, 350 mhz bw direct coupled fully differential signal path logarithmic slope, intercept and ac response are stable over full military temperature range dual polarity current outputs scaled 1 ma/decade voltage slope options (1 v/decade, 100 mv/db, etc.) low power operation (typically 220 mw at 6 5 v) low cost plastic packages also available applications radar, sonar, ultrasonic and audio systems precision instrumentation from dc to 120 mhz power measurement with absolute calibration wide range high accuracy signal compression alternative to discrete and hybrid if strips replaces several discrete log amp ics product description the ad640 is a complete monolithic logarith mic amplifier. a single ad640 provides up to 50 db of dynamic range for frequencies from dc to 120 mhz. two ad640s in cascade can provide up to 95 db of dynamic range at reduced bandwidth. the ad640 uses a successive detection scheme to provide an output current propor- tional to the logarithm of the input voltage. it is laser calibrated to close tolerances and maintains high accuracy over the full military temperature range using supply voltages from 4.5 v to 7.5 v. the ad640 comprises five cascaded dc-coupled amplifier/limiter stages, each having a small signal voltage gain of 10 db and a C3 db bandwidth of 350 mhz. each stage has an associated full-wave detector, whose output current depends on the absolute value of its input voltage. the five outputs are summed to provide the video output (when low-pass filtered) scaled at 1 ma per decade (50 m a per db). on chip resistors can be used to convert this output cur- rent to a voltage with several convenient slope options. a balanced signal output at +50 db (referred to input) is provided to operate ad640s in cascade. the logarithmic response is absolutely calibrated to within 1 db for dc or square wave inputs from 0.75 mv to 200 mv, with an intercept (logarithmic offset) at 1 mv dc. an integral x10 attenuator provides an alternative input range of 7.5 mv to 2 v dc. scaling is also guaranteed for sinusoidal inputs. the ad640b is specified for the industrial temperature range of C40 c to +85 c and the ad640t, available processed to mil- std-883b, for the military range of C55 c to +125 c. both are available in 20-lead side-brazed ceramic dips or leadless chip carriers (lcc). the ad640j is specified for the commercial temperature range of 0 c to +70 c, and is available in both 20-lead plastic dip (n) and plcc (p) packages. this device is now available to standard military drawing (desc) number 5962-9095501mra and 5962-9095501m2a. product highlights 1. absolute calibration of a wideband logarithmic amplifier is unique. the ad640 is a high accuracy measurement device, not simply a logarithmic building block. 2. advanced design results in unprecedented stability over the full military temperature range. 3. the fully differential signal path greatly reduces the risk of instability due to inadequate power supply decoupling and shared ground connections, a serious problem with com- monly used unbalanced designs. 4. differential interfaces also ensure that the appropriate ground connection can be chosen for each signal port. they further increase versatility and simplify applications. the signal input impedance is ~500 k w in shunt with ~2 pf. 5. the dc-coupled signal path eliminates the need for numerous interstage coupling capacitors and simplifies logarithmic conversion of subsonic signals. ( continued on page 4) functional block diagram rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices.
ad640Cspecifications dc specifications model ad640j ad640b ad640t parameter conditions min typ max min typ max min typ max units transfer function 1 i out = i y log |v in /v x | for v in = 0.75 mv to 200 mv dc signal inputs (pins 1, 20) input resistance differential 500 500 500 k w input offset voltage differential 50 500 50 200 50 200 m v vs. temperature 0.8 0.8 0.8 m v/ c over temperature t min to t max 300 m v vs. supply 2 2 2 m v/v input bias current 7 25 7 25 7 25 m a input bias offset 1 1 1 m a common-mode range C2 +0.3 C2 +0.3 C2 +0.3 v input attenuator (pins 2, 3, 4, 5 and 19) attenuation 2 pin 5 to pin 19 20 20 20 db input resistance pins 5 to 3/4 300 300 300 w signal output (pins 10, 11) small signal gain 3 50 50 50 db peak differential output 4 180 180 180 mv output resistance either pin to com 75 75 75 w quiescent output voltage either pin to com C90 C90 C90 mv logarithmic output 5 (pin 14) voltage compliance range C0.3 +v s C1 C0.3 +v s C1 C0.3 v s C1 v slope current, i y 0.95 1.00 1.05 0.98 1.00 1.02 0.98 1.00 1.02 ma accuracy vs. temperature 0.002 0.002 0.002 %/ c t min to t max 0.9 6 1.02 ma accuracy vs. supply +v s = 4.5 v to 7.5 v 0.08 1.0 0.08 0.4 0.08 0.4 %/v intercept voltage 6 , v x 0.85 0 . 99 1.15 0.9 3 0 . 99 1.05 0.9 3 0.99 1.05 mv vs. temperature 0.5 0.5 0.5 m v/ c over temperature t min to t max 0.90 1.10 mv vs. supply v s = 4.5 v to 7.5 v 2 2 2 m v/v logarithmic offset (alt. definition of v x ) C61.5 C60.0 C58.7 C60.5 C60.0 C59.5 C60.5 C60.0 C59.5 dbv vs. temperature 0.004 0.004 0.004 db/ c over temperature t min to t max C60.9 C59.1 db vs. supply v s = 4.5 v to 7.5 v 0.017 0.017 0.017 db/v intercept voltage using attenuator 8.25 10.0 11.75 9.0 10.0 11.0 9.0 10.0 11.0 mv zero signal output current 7 C0.2 C0.2 C0.2 ma itc disabled pin 8 to com C0.27 C0.27 C0.27 ma maximum output current 2.3 2.3 2.3 ma applications resistors (pins 15, 16, 17) 1.000 0.995 1.000 1.005 0.995 1.000 1.005 k w dc linearity v in 1 mv to 100 mv 0.35 1.2 0.35 0.6 0.35 0.6 db total absolute dc accuracy v in = 1 mv to 100 mv 8 0.55 2 0.55 1 . 2 0.55 1 . 2 db over temperature t min to t max 3 2 . 0 2 . 0 db over supply range v s = 4.5 v to 7.5 v 2 1. 5 1. 5 db v in = 0.75 mv to 200 mv 1.0 3 1.0 2.0 1.0 2.0 db using attenuator v in = 10 mv to 1 v 0.4 2.5 0.4 1.5 0.4 1.5 db over temperature t min to t max 0.6 3 0.6 2. 2 0.6 2. 2 db v in = 7.5 mv to 2 v 1.2 3.5 1.2 2.5 1.2 2.5 db power requirements voltage supply range 6 4.5 6 7.5 6 4.5 6 7.5 6 4.5 6 7.5 v quiescent current 9 +v s (pin 12) t min to t max 915 9 15 9 15 ma Cv s (pin 7) t min to t max 35 60 35 60 35 60 ma C2C rev. d (v s = 6 5 v, t a = +25 8 c, unless otherwise noted)
ac specifications model ad640j ad640b ad640t parameter conditions min typ max min typ max min typ max units signal inputs (pins 1, 20) input capacitance either pin to com 2 2 2 pf noise spectral density 1 khz to 10 mhz 2 2 2 nv/ ? hz tangential sensitivity bw = 100 mhz C72 C72 C72 dbm 3 db bandwidth each stage 350 350 350 mhz all five stages pins 1 & 20 to 10 & 11 145 145 145 mhz logarithmic outputs 5 slope current, i y f< = 1 mhz 0.96 1.0 1.04 0.98 1.0 1.02 0.98 1.0 1.02 ma f = 30 mhz 0.88 0.94 1.00 0.91 0.94 0.97 0.91 0.94 0.97 ma f = 60 mhz 0.82 0.90 0.98 0.86 0.90 0.94 0.86 0.90 0.94 ma f = 90 mhz 0.88 0.88 0.88 ma f = 120 mhz 0.85 0.85 0.85 ma intercept, dual ad640s 10, 11 f< = 1 mhz C 90.6 C88.6 C86.6 C 90 . 0 C88.6 C87.6 C 90 . 0 C88.6 C87.6 dbm f = 30 mhz C87.6 C87.6 C87.6 dbm f = 60 mhz C86.3 C86.3 C86.3 dbm f = 90 mhz C83.9 C83.9 C83.9 dbm f = 120 mhz C80.3 C80.3 C80.3 dbm ac linearity C40 dbm to C2 dbm 12 f = 1 mhz 0.5 2.0 0.5 1.0 0.5 1.0 db C35 dbm to C10 dbm 12 f = 1 mhz 0.25 1.0 0.25 0.5 0.25 0.5 db C75 dbm to 0 dbm 10 f = 1 mhz 0.75 3.0 0.75 1.5 0.75 1.5 db C70 dbm to C10 dbm 10 f = 1 mhz 0.5 2.0 0.5 1.0 0.5 1.0 db C75 dbm to +15 dbm 13 f = 10 khz 0.5 3.0 0.5 1.5 0.5 1.5 db package option ad640td ad640be ad640te ad640]n 20-lead ceramic sb dip package (d) 20-terminal ceramic lcc (e) 20-lead plastic dip package (n) 20-lead plastic leaded chip carrier ( p) ad640jp ad640bp number of transistors 155 155 155 notes 1 logarithms to base 10 are used throughout. the response is independent of the sign of v in . 2 attenuation ratio trimmed to calibrate intercept to 10 mv when in use. it has a temperature coefficient of +0.30%/ c. 3 overall gain is trimmed using a 200 m v square wave at 2 khz, corrected for the onset of compression. 4 the fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute temperature. 5 currents defined as flowing into pin 14. see fundamentals of logarithmic conversion for full explanation of scaling concepts. slope is measured by linear regression over central region of transfer function. 6 the logarithmic intercept in dbv (decibels relative to 1 v) is defined as 20 log 10 (v x /1 v). 7 the zero-signal current is a function of temperature unless internal temperature compensation (itc) pin is grounded. 8 operating in circuit of figure 24 using 0.1% accurate values for r la and r lb. includes slope and nonlinearity errors. input offset errors also included for v in >3 mv dc, and over the full input range in ac applications. 9 essentially independent of supply voltages. 10 using the circuit of figure 27, using cascaded ad640s and offset nulling. input is sinusoidal, 0 dbm in 50 w = 223 mv rms. 11 for a sinusoidal signal (see effect of waveform on intercept). pin 8 on second ad640 must be grounded to ensure temperature stability of intercept for dual ad640 system. 12 using the circuit of figure 24, using single ad640 and offset nulling. input is sinusoidal, 0 dbm in 50 w = 223 mv rms. 13 using the circuit of figure 32, using cascaded ad640s and attenuator. square wave input. all min and max specifications are guaranteed, but only those in boldface are 100% tested on all production units. results from those tests are used to calculate outgoing quality levels. specifications subject to change without notice. thermal characteristics u jc ( 8 c/w) u ja ( 8 c/w) 25 85 25 85 24 61 20-lead ceramic sb dip package (d-20) 20-terminal ceramic lcc (e-20 -1) 20-lead plastic dip package (n-20) 20-lead plastic leaded chip carrier (p-20) 28 75 ad640 rev. d C3C (v s = 6 5 v, t a = +25 8 c, unless otherwise noted)
ad640 rev. d C4C chip dimensions and bonding diagram dimensions shown in inches and (mm). absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 v input voltage (pin 1 or pin 20 to com) . . . . C3 v to +300 mv attenuator input voltage (pin 5 to pin 3/4) . . . . . . . . . . . 4 v storage temperature range d, e . . . . . . . . . C65 c to +150 c storage temperature range n, p . . . . . . . . . C65 c to +125 c ambient temperature range, rated performance industrial, ad640b . . . . . . . . . . . . . . . . . . . C40 c to +85 c military, ad640t . . . . . . . . . . . . . . . . . . . C55 c to +125 c commercial, ad640j . . . . . . . . . . . . . . . . . . . 0 c to +70 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ( continued from page 1) 6. the low input offset voltage of 50 m v (200 m v max) ensures good accuracy for low level dc inputs. 7. thermal recovery tails, which can obscure the response when a small signal immediately follows a high level input, have been minimized by special attention to design details. 8. the noise spectral density of 2 nv/ ? hz results in a noise floor of ~23 m v rms (C80 dbm) at a bandwidth of 100 mhz. the dy- namic range using cascaded ad640s can be extended to 95 db by the inclusion of a simple filter between the two devices. esd caution connection diagrams 20-lead plcc (p) package 20-terminal ceramic lcc (e) package 20-lead ceramic sb dip (d) package 20-lead plastic dip (n) package 9 10 11 12 13 3 2 1 20 19 18 17 16 15 14 4 5 6 7 8 top view (not to scale) pin 1 identifier ad640 atn com ckt com atn com atn lo bl2 sig Cin sig +in atn out rg1 rg0 rg2 log out sig Cout sig +out +v s log com atn in bl1 Cv s itc top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ad640 sig Cout bl2 itc atn lo atn com atn com Cv s bl1 atn in sig Cin sig +in atn out ckt com rg1 rg0 rg2 log out log com +v s sig +out 20 19 1 2 3 18 14 15 16 17 4 5 6 7 8 9 10111213 top view (not to scale) ad640 atn com ckt com atn com atn lo bl2 sig Cin sig +in atn out rg1 rg0 rg2 log out sig Cout sig +out +v s log com atn in bl1 Cv s itc
typical dc performance characteristicsCad640 rev. d C5C 1.015 1.010 1.005 1 0.995 0.990 0.985 0.980 C60 C40 C20 0 20 40 60 80 100 120 140 temperature C 8c slope current C ma figure 1. slope current, i y vs. temperature 4.5 5.0 5.5 6.0 6.5 7.0 7.5 power supply voltages C 6 volts intercept voltage C mv 1.015 1.010 1.005 1.000 0.995 0.990 0.985 figure 4. intercept voltage, v x , vs. supply voltages input voltage C mv (either sign) output current C ma 2 1.0 0.1 1.0 1000.0 10.0 100.0 1 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0.8 0.6 0.4 0.2 0 C0.2 C0.4 error C db 0 figure 7. dc logarithmic transfer function and error curve for single ad640 1.20 1.15 1.10 1.05 1.00 0.95 0.90 C60 C40 C20 0 20 40 60 80 100 120 140 temperature C 8c intercept C mv 0.85 figure 2. intercept voltage, v x , vs. temperature 14 13 12 11 10 9 8 7 C60 C40 C20 0 20 40 60 80 100 120 140 temperature C 8c intercept C mv figure 5. intercept voltage (using attenuator) vs. temperature 2.5 2.0 1.5 1.0 0.5 C60 C40 C20 0 20 40 60 80 100 120 140 temperature C 8c 0 absolute error C db figure 8. absolute error vs. tem- perature, v in = 6 1 mv to 6 100 mv 4.5 5.0 5.5 6.0 6.5 7.0 7.5 power supply voltages C 6 volts slope current C ma 1.006 1.004 1.002 1.000 0.998 0.996 0.994 figure 3. slope current, i y vs. supply voltages C60 C40 C20 0 20 40 60 80 100 120 140 temperature C 8c deviation of input offset voltage C mv 0 C0.1 +0.4 +0.3 +0.2 +0.1 C0.2 C0.3 input offset voltage deviation will be within shaded area. figure 6. input offset voltage deviation vs. temperature 2.5 2.0 1.5 1.0 0.5 C60 C40 C20 0 20 40 60 80 100 120 140 temperature C 8c 0 absolute error C db figure 9. absolute error vs. temperature, using attenuator. v in = 6 10 mv to 6 1 v, pin 8 grounded to disable itc bias
ad640 rev. d C6C input level C dbm C2.5 C2.0 0.5 C40 C0.5 0 C1.5 C1.0 output current C ma C50 C30 C20 C10 0 30mhz 60mhz 90mhz 120mhz ad640 6 v s = 5 volts temperature = +258c figure 10. ac response at 30 mhz, 60 mhz, 90 mhz and 120 mhz, vs. dbm input (sinusoidal input) frequency C mhz 1.0 dc 30 slope current C ma 0.95 0.90 0.85 0.80 60 90 120 150 figure 11. slope current, i y , vs. input frequency figure 12. baseband pulse response of single ad640, inputs of 1 mv, 10 mv and 100 mv +258c +1258c C558c +1258c C558c +258c +1258c C558c C558c input level C dbm C2.5 0 C50 0 output current C ma C2.0 C1.5 C1.0 C5 0.5 C40 C30 C20 C10 +1 0 C1 C2 +1258c +258c ad640 frequency = 60mhz error in db figure 13. logarithmic response and linearity at 60 mhz, t a for t a = C55 8 c, +25 8 c, +125 8 c input frequency C mhz intercept level C dbm 90 80 0 120 10 20 100 110 89 87 86 85 84 88 30 40 50 60 70 80 90 83 82 81 figure 14. intercept level (dbm) vs. frequency (cascaded ad640s C sinusoidal input) 10 0% 5s 5s 20mv 20mv 100 90 figure 15. baseband pulse response of cascaded ad640s, inputs of 0.2 mv, 2 mv, 20 mv and 200 mv Ctypical ac performance characteristics
ad640 rev. d C7C circuit description the ad640 uses five cascaded limiting amplifiers to approxi- mate a logarithmic response to an input signal of wide dynamic range and wide bandwidth. this type of logarithmic amplifier has traditionally been assembled from several small scale ics and numerous external components. the performance of these semidiscrete circuits is often unsatisfactory. in particular, the loga rithmic slope and intercept (see fundamentals of logarithmic conversion) are usually not very stable in the presence of supply and temperature variations even after laborious and expensive individual calibration. the ad640 employs high precision analog circuit techniques to ensure sta- bility of scaling over wide variations in supply voltage and tem- perature. laser trimming, using ac stimuli and operating conditions similar to those encountered in practice, pr ovides fully calibrated logarithmic conversion. each of the amplifier/limiter stages in the ad640 has a small signal voltage gain of 10 db ( 3.162) and a C3 db bandwidth of 350 mhz. fully differential direct coupling is used throughout. this eliminates the many interstage coupling capacitors usually required in ac applications, and simplifies low frequency signal processing, for example, in audio and sonar systems. the ad640 is intended for use in demodulating applications. each stage incorporates a detector (a full wave transconductance rectifier) whose output current depends on the absolute value of its input voltage. figure 16 is a simplified schematic of one stage of the ad640. all transistors in the basic cell operate at near zero collector to base voltage and low bias currents, resulting in low levels of ther- mally induced distortion. these arise when power shifts from one set of tran sistors to another during large input signals. rapid recovery is essential when a small signal immediately follows a large one. this low power operation also contributes signifi- cantly to the excellent long-term calibration stability of the ad640. the complete ad640, shown in figure 17, includes two bias regulators. one determines the small signal gain of the amplifier stages; the other determines the logarithmic slope. these bias regulators maintain a high degree of stability in the resulting function by compensating for potentially large uncertainties in transistor parameters, temperature and supply voltages. a third biasing block is used to accurately control the logarithmic intercept. by summing the signals at the output of the detectors, a good approximation to a logarithmic transfer function can be achieved. the lower the stage gain, the more accurate the approximation, but more stages are then needed to cover a given dynamic range. the choice of 10 db results in a theoretical periodic q3 q4 q5 q6 q7 q8 1.09ma ptat 1.09ma ptat r2 85v 565ma q2 r1 85v q1 q9 log out 565ma q10 log com 2.18ma ptat r4 75v r3 75v sig out sig in common Cv s figure 16. simplified schematic of a single ad640 stage deviation or ripple in the transfer function of 0.15 db from the ideal response when the input is either a dc voltage or a square wave. the slope of the transfer function is unaffected by the input waveform; however, the intercept and ripple are waveform dependent (see effect of waveform on intercept). the input will usually be an amplitude modulated sinusoidal carrier. in these circumstances the output is a fluctuating current at twice the carrier frequency (because of the full wave detection) whose average value is extracted by an external low-p ass filter, which recovers a logarithmic measure of the baseband signal. circuit operation with reference to figure 16, the transconductance pair q7, q8 and load resistors r3 and r4 form a limiting amplifier having a small signal gain of 10 db, set by the tail current of nominally 2.18 ma at 27 c. this current is basically proportional to abso- lute temperature (ptat) but includes additional current to compensate for finite beta and junction resistance. the limiting output voltage is 180 mv at 27 c and is ptat. emitter fol- lowers q1 and q2 raise the input resistance of the stage, provide level shifting to introduce collector bias for the gain stage and detectors, reduce offset drift by forming a thermally balanced quad with q7 and q8 and generate the detector biasing across resistors r1 and r2. transistors q3 through q6 form the full wave detector, whose output is buffered by the cascodes q9 and q10. for zero input q3 and q5 conduct only a small amount (a total of about 32 m a) of the 565 m a tail currents supplied to pairs q3Cq4 and q5Cq6. this pedestal current flows in output cascode q9 to the log out node (pin 14). when driven to the peak output of the preceding stage, q3 or q5 (depending on signal polarity) conducts lost of the tail current, and the output rises to 532 m a. the log out current has thus changed by 500 m a as the input has changed from zero to its maximum value. since the detectors are spaced at 10 db intervals, the output increases by atn out amplifier/limiter full-wave detector atn lo atn com sig +in sig Cin atn com com 27v 30v 270v atn in 1kv rg1 rg0 rg2 Cv s bl1 +v s log out log com sig +out sig Cout bl2 itc 20 1 intercept positioning bias 19 3 2 4 18 5 6 gain bias regulator amplifier/limiter full-wave detector amplifier/limiter full-wave detector 10db amplifier/limiter full-wave detector 10db 10db amplifier/limiter full-wave detector 17 16 14 13 1kv 7 11 10 9 8 12 slope bias regulator 15 10db 10db figure 17. block diagram of the complete ad640
ad640 rev. d C8C 50 m a/db, or 1 ma per decade. this scaling parameter is trimmed to absolute accuracy using a 2 khz square wave. at frequencies near the system bandwidth, the slope is reduced due to the reduced output of the limiter stages, but it is still rela- tively insensitive to temperature variations so that a simple ex- ternal slope adjustment in restore scaling accuracy. the intercept position bias generator (figure 17) removes the pedestal current from the summed detector outputs. it is ad- justed during manufacture such that the output (flowing into pin 14) is 1 ma when a 2 khz square-wave input of exactly 10 mv is applied to the ad640. this places the dc intercept at precisely 1 mv. the log com output (pin 13) is the comple- ment of log out. it also has a 1 mv intercept, but with an inverted slope of C1 ma/decade. because its pedestal is very large (equivalent to about 100 db), its intercept voltage is not guaranteed. the intercept positioning currents include a special internal temperature compensation (itc) term which can be disabled by connecting pin 8 to ground. the logarithmic function of the ad640 is absolutely calibrated to within 0.3 db (or 15 m a) for 2 khz square-wave inputs of 1 mv to 100 mv, and to within 1 db between 750 m v and 200 mv. figure 18 is a typical plot of the dc transfer function, showing the outputs at temperatures of C55 c, +25 c and +125 c. while the slope and intercept are seen to be little af- fected by temperature, there is a lateral shift in the endpoints of the linear region of the transfer function, which reduces the effective dynamic range. the cause of this shift is explained in fundamentals of logarithmic conversion section. input voltage C mv 2.5 0 0.1 output current C ma 1.0 10.0 100.0 1000.0 2 1 0 C1 C2 2.0 1.5 1.0 0.5 C0.5 +1258c +258c C558c +258c +1258c C558c absolute error C db figure 18. logarithmic output and absolute error vs. dc or square wave input at t a = C55 c, +25 c, input direct to pins 1 and 20 the on chip attenuator can be used to handle input levels 20 db higher, that is, from 7.5 mv to 2 v for dc or square wave inputs. it is specially designed to have a positive temperature coefficient and is trimmed to position the intercept at 10 mv dc (or C24 dbm for a sinusoidal input) over the full temperature range. when using the attenuator the internal bias compensa- tion should be disabled by grounding pin 8. figure 19 shows the output at C55 c, +25 c, +85 c and +125 c for a single ad640 with the attenuator in use; the curves overlap almost perfectly, and the lateral shift in the transfer function does not occur. therefore, the full dynamic range is available at all temperatures. the output of the final limiter is available in differential form at pins 10 and 11. the output impedance is 75 w to ground from either pin. for most input levels, this output will appear to have input voltage C mv 2.5 0 1 output current C ma 10 100 1000 10000 1 0 C1 C2 2.0 1.5 1.0 0.5 C0.5 +258c +858c +1258c C558c absolute error C db figure 19. logarithmic output and absolute error vs. dc or square wave input at t a = C55 c, +25 c, +85 c and +125 c, input via on-chip attenuator roughly a square waveform. the signal path may be extended using these outputs (see operation of cascaded ad640s). the logarithmic outputs from two or more ad640s can be directly summed with full accuracy. a pair of 1 k w applications resistors, rg1 and rg2 (figure 17) are accessed via pins 15, 16 and 17. t hese can be used to con- vert an output current to a voltage, with a slope of 1 v/decade (using one resistor), 2 v/decade (both resistors in series) or 0.5 v/decade (both in parallel). using all the resistors from two ad640s (for example, in a cascaded configuration) ten slope options from 0.25 v to 4 v/decade are available. fundamentals of logarithmic conversion the conversion of a signal to its equivalent logarithmic value involves a nonlinear operation, the consequences of which can be very confusing if not fully understood. it is important to realize from the outset that many of the familiar concepts of linear circuits are of little relevance in this context. for example, the incremental gain of an ideal logarithmic converter approaches infinity as the input approaches zero. further, an offset at the output of a linear amplifier is simply equivalent to an offset at the input, while in a logarithmic converter it is equivalent to a change of amplitude at the inputa very different relationship. we assume a dc signal in the following discussion to simplify the concepts; ac behavior and the effect of input waveform on cali- bration are discussed later. a logarithmic converter having a voltage input v in and output v out must satisfy a transfer func- tion of the form v out = v y log ( v in /v x ) equation (1) where vy and vx are fixed voltages which determine the scaling of the converter. the input is divided by a voltage because the argument of a logarithm has to be a simple ratio. the logarithm must be multiplied by a voltage to develop a voltage output. these operations are not, of course, carried out by explicit com- putational elements, but are inherent in the behavior of the converter. for stable operation, v x and v y must be based on sound design criteria and rendered stable over wide temperature and supply voltage extremes. this aspect of rf logarithmic amplifier design has traditionally received little attention. when v in = v x , the logarithm is zero. v x is, therefore, called the intercept voltage, because a graph of v out versus log (v in ) ideally a straight linecrosses the horizontal axis at this point
ad640 rev. d C9C (see figure 20). for the ad640, v x is calibrated to exactly 1 mv. the slope of the line is directly proportional to v y . base 10 logarithms are used in this context to simplify the relation- ship to decibel values. for v in = 10 v x , the logarithm has a value of 1, so the output voltage is v y . at v in = 100 v x , the output is 2 v y , and so on. v y can therefore be viewed either as the slope voltage or as the volts per decade factor. 0 v y 2v y v in = v x v in = 10v x v in = 100v x slope = v y actual ideal input on log scale actual ideal v y log (v in /v x ) figure 20. basic dc transfer function of the ad640 the ad640 conforms to equation (1) except that its two out- puts are in the form of currents, rather than voltages: i out = i y log ( v in / v x ) equation (2) i y the slope current, is 1 ma. the current output can readily be converted to a voltage with a slope of 1 v/decade, for example, using one of the 1 k w resistors provided for this purpose, in conjunction with an op amp, as shown in figure 21. 11 15 14 13 12 6 7 8 9 10 sig +out log com log out +v s Cv s itc bl2 sig Cout ad640 c1 330pf ad844 r1 48.7v r2 1ma per decade output voltage 1v per decade for r2 = 1kv 100mv per db for r2 = 2k v figure 21. using an external op amp to convert the ad640 output current to a buffered voltage output intercept stabilization internally, the intercept voltage is a fraction of the thermal volt- age kt/q, that is, v x = v xo t/t o , where v xo is the value of v x at a reference temperature t o . so the uncorrected transfer function has the form i out = i y log ( v in t o /v xo t ) equation (3) now, if the amplitude of the signal input v in could somehow be rendered ptat, the intercept would be stable with tempera- ture, since the temperature dependence in both the numerator and denominator of the logarithmic argument would cancel. this is what is actually achieved by interposing the on-chip attenuator, which has the necessary temperature dependence to cause the input to the first stage to vary in proportion to abso- lute temperature. the end limits of the dynamic range are now totally independent of temperature. consequently, this is the preferred method of intercept stabilization for applications where the input signal is sufficiently large. when the attenuator is not used, the ptat variation in v x will result in the intercept being temperature dependent. near 300k (27 c) it will vary by 20 log (301/300) db/ c, about 0.03 db/ c. unless corrected, the whole output function would drift up or down by this amount with changes in temperature. in the ad640 a temperature compensating current i y log(t/t o ) is added to the output. this effectively maintains a constant intercept v xo . this correction is active in the default state (pin 8 open circuited). when using the attenuator, pin 8 should be grounded, which disables the compensation current. the drift term needs to be compensated only once; when the outputs of two ad540s are summed, pin 8 should be grounded on at least one of the two devices (both if the attenuator is used). conversion range practical logarithmic converters have an upper and lower limit on the input, beyond which errors increase rapidly. the upper limit occurs when the first stage in the chain is driven into limit- ing. above this, no further increase in the output can occur and the transfer function flattens off. the lower limit arises because a finite number of stages provide finite gain, and therefore at low signal levels the system becomes a simple linear amplifier. note that this lower limit is not determined by the intercept voltage, v x ; it can occur either above or below v x , depending on the design. when using two ad640s in cascade, input offset voltage and wideband noise are the major limitations to low level accuracy. offset can be eliminated in various ways. noise can only be reduced by lowering the system bandwidth, using a filter between the two devices. effect of waveform on intercept the absolute value response of the ad640 allows inputs of either polarity to be accepted. thus, the logarithmic output in response to an amplitude-symmetric square wave is a steady value. for a sinusoidal input the fluctuating output current will usually be low-pass filtered to extract the baseband signal. the unfiltered output is at twice the carrier frequency, simplifying the design of this filter when the video bandwidth must be maxi- mized. the averaged output depends on waveform in a roughly analogous way to waveform dependence of rms value. the effect is to change the apparent intercept voltage. the intercept volt- age appears to be doubled for a sinusoidal input, that is, the averaged output in response to a sine wave of amplitude (not rms value) of 20 mv would be the same as for a dc or square wave input of 10 mv. other waveforms will result in different inter- cept factors. an amplitude-symmetric-rectangular waveform has the same intercept as a dc input, while the average of a baseband unipolar pulse can be determined by multiplying the response to a dc input of the same amplitude by the duty cycle. it is important to understand that in responding to pulsed rf signals it is the waveform of the carrier (usually sinusoidal) not the modulation envelope, that determines the effective intercept voltage. table i shows the effective intercept and resulting deci- bel offset for commonly occurring waveforms. the input wave- form does not affect the slope of the transfer function. figure 22 shows the absolute deviation from the ideal response of cascaded ad640s for three common waveforms at input levels from C80 dbv to C10 dbv. the measured sine wave and triwave responses are 6 db and 8.7 db, respectively, below the square wave responsein agreement with theory.
ad640 rev. d C10C table i. input peak intercept error (relative waveform or rms factor to a dc input) square wave either 1 0.00 db sine wave peak 2 C6.02 db sine wave rms 1.414( ? 2 ) C3.01 db triwave peak 2.718 (e) C8.68 db triwave rms 1.569(e/ ? 3 ) C3.91 db gaussian noise rms 1.887 C5.52 db logarithmic conformance and waveform the waveform also affects the ripple, or periodic deviation from an ideal logarithmic response. the ripple is greatest for dc or square wave inputs because every value of the input voltage maps to a single location on the transfer function and thus traces out the full nonlinearities in the logarithmic response. by contrast, a general time varying signal has a continuum of values within each cycle of its waveform. the averaged output is thereby smoothed because the periodic deviations away from the ideal response, as the waveform sweeps over the transfer function, tend to cancel. this smoothing effect is greatest for a triwave input, as demonstrated in figure 22. input amplitude in db above 1v, at 10khz 2 C10 C80 deviation from exact logarithmic transfer function C db C8 C6 C4 C2 0 C70 C60 C50 C40 C30 C20 C10 square wave input sine wave input triwave input figure 22. deviation from exact logarithmic transfer function for two cascaded ad640s, showing effect of waveform on calibration and linearity input amplitude in db above 1v, at 10khz 2 C10 deviation from exact logarithmic transfer function C db C8 C6 C4 C2 0 C70 C60 C50 C40 C30 C20 C10 square wave input sine wave input triwave input C12 4 figure 23. deviation from exact logarithmic transfer function for a single ad640; compare low level response with that of figure 22 the accuracy at low signal inputs is also waveform dependent. the detectors are not perfect absolute value circuits, having a sharp corner near zero; in fact they become parabolic at low levels and behave as if there were a dead zone. consequently, the output tends to be higher than ideal. when there are enough stages in the system, as when two ad640s are connected in cascade, most detectors will be adequately loaded due to the high overall gain, but a single ad640 does not have sufficient gain to maintain high accuracy for low level sine wave or triwave inputs. figure 23 shows the absolute deviation from calibration for the same three waveforms for a single ad640. for inputs between C10 dbv and C40 dbv the vertical displacement of the traces for the various waveforms remains in agreement with the predicted dependence, but significant calibration errors arise at low signal levels. signal magnitude ad640 is a calibrated device. it is, therefore, important to be clear in specifying the signal magnitude under all waveform conditions. for dc or square wave inputs there is, of course, no ambiguity. bounded periodic signals, such as sinusoids and triwaves, can be specified in terms of their simple amplitude (peak value) or alternatively by their rms value (which is a mea- sure of power when the impedance is specified). it is generally bet- ter to define this type of signal in terms of its amplitude because the ad640 response is a consequence of the input voltage, not power. however, provided that the appropriate value of inter- cept for a specific waveform is observed, rms measures may be used. random waveforms can only be specified in terms of rms value because their peak value may be unbounded, as is the case for gaussian noise. these must be treated on a case-by-case basis. the effective intercept given in table i should be used for gaussian noise inputs. on the other hand, for bounded signals the amplitude can be expressed either in volts or dbv (decibels relative to 1 v). for example, a sine wave or triwave of 1 mv amplitude can also be defined as an input of C60 dbv, one of 100 mv amplitude as C20 dbv, and so on. rms value is usually expressed in dbm (decibels above 1 mw) for a specified impedance level. through- out this data sheet we assume a 50 w environment, the customary impedance level for high speed systems, when referring to signal power in dbm. bearing in mind the above discussion of the effect of waveform on the intercept calibration of the ad640, it will be apparent that a sine wave at a power of, say, C10 dbm will not produce the same output as a triwave or square wave of the same power . thus, a sine wave at a power level of C10 dbm has an rms value of 70.7 mv or an amplitude of 100 mv (that is, ? 2 times as large, the ratio of amplitude to rms value for a sine wave), while a triwave of the same power has an amplitude which is ? 3 or 1.73 times its rms value, or 122.5 mv. intercept and logarithmic offset if the signals are expressed in dbv, we can write the output in a simpler form, as i out = 50 m a ( input dbv C x dbv ) equation (4) where input dbv is the input voltage amplitude (not rms) in dbv and x dbv is the appropriate value of the intercept (for a given waveform) in dbv. this form shows more clearly why the inter cept is often referred to as the logarithmic offset. for dc or square wave inputs, v x is 1 mv so the numerical value of x dbv is C60, and equation (4) becomes
ad640 rev. d C11C i out = 50 m a ( input dbv + 60) equation (5) alternatively, for a sinusoidal input measured in dbm (power in db above 1 mw in a 50 w system) the output can be written i out = 50 m a ( input dbm + 44) equation (6) because the intercept for a sine wave expressed in volts rms is at 1.414 mv (from table i) or C44 dbm. operation of a single ad640 figure 24 shows the basic connections for a single device, using 100 w load resistors. output a is a negative going voltage with a slope of C100 mv per decade; output b is positive going with a slope of +100 mv per decade. for applications where absolute calibration of the intercept is essential, the main output (from log out, pin 14) should be used; the log com output can then be grounded. to evaluate the demodulation response, a simple low-pass output filter having a time constant of roughly 500 m s (3 db corner of 320 hz) is provided by a 4.7 m f (C20% +80%) ceramic capacitor (erie type rpe117-z5u-475-k50v) placed across the load. a dvm may be used to measure the averaged output in verification tests. the voltage compliance at pins 13 and 14 extends from 0.3 v below ground up to 1 v below +v s . since the current into pin 14 is from C0.2 ma at zero signal to +2.3 ma when fully limited (dc input of >300 mv) the output never drops below C230 mv. on the other hand, the current out of pin 13 ranges from 0.2 ma to +2.3 ma, and if desired, a load resistor of up to 2 k w can be used on this output; the slope would then be 2 v per decade. use of the log com output in this way provides a numerically correct decibel read- ing on a dvm (+100 mv = +1.00 db). board layout is very important. the ad640 has both high gain and wide bandwidth; therefore every signal path must be very carefully considered. a high quality ground plane is essential, but it should not be assumed that it behaves as an equipotential plane. even though the application may only call for modest bandwidth, each of the three differential signal interface pairs (sig in, pins 1 and 20, sig out, pins 10 and 11, and log, pins 13 and 14) must have their own starred ground points to avoid oscillation at low signal levels (where the gain is highest). unused pins (excluding pins 8, 10 and 11) such as the attenua- tor and applications resistors should be grounded close to the package edge. bl1 (pin 6) and bl2 (pin 9) are internal bias lines a volt or two above the Cv s node; access is provided solely for the addition of decoupling capacitors, which should be con- nected exactly as shown (not all of them connect to the ground). use low impedance ceramic 0.1 m f capacitors (for example, erie rpe113-z5u-105-k50v). ferrite beads may be used instead of supply decoupling resistors in cases where the supply voltage is low. active current-to-voltage conversion the compliance at log out limits the available output volt- age swing. the output of the ad640 may be converted to a larger, buffered output voltage by the addition of an operational amplifier connected as a current-to-voltage (transresistance) stage, as shown in figure 21. using a 2 k w feedback resistor (r2) the 50 m a/db output at log out is converted to a volt- age having a slope of +100 mv/db, that is, 2 v per decade. this output ranges from roughly C0.4 v for zero signal inputs to the ad640, crosses zero at a dc input of precisely +1 mv (or C1 mv) and is +4 v for a dc input of 100 mv. a passive prefilter, formed by r1 and c1, minimizes the high frequency energy conveyed to the op amp. the corner frequency is here shown as 10 mhz. the ad844 is recommended for this appli- cation because of its excellent performance in transresistance modes. its bandwidth of 35 mhz (with the 2 k w feedback resis- tor) will exceed the baseband response of the system in most applications. for lower bandwidth applications other op amps and multipole active filters may be substituted (see, for example, figure 32 in the applications section). effect of frequency on calibration the slope and intercept of the ad640 are calibrated during manufacture using a 2 khz square wave input. calibration de- pends on the gain of each stage being 10 db. when the input frequency is an appreciable fraction of the 350 mhz bandwidth of the amplifier stages, their gain becomes imprecise and the logarithmic slope and intercept are no longer fully calibrated. however, the ad640 can provide very stable operation at fre- quencies up to about one half the 3 db frequency of the ampli- fier stages. figure 10 shows the averaged output current versus input level at 30 mhz, 60 mhz, 90 mhz and 120 mhz. fig- ure 11 shows the absolute error in the response at 60 mhz and at temperatures of C55 c, +25 c and +125 c. figure 12 shows the variation in the slope current, and figure 13 shows the variat ion in the intercept level (sinusoidal input) versus frequency. if absolute calibration is essential, or some other value of slope or intercept is required, there will usually be some point in the users system at which an adjustment may be easily introduced. for example, the 5% slope deficit at 30 mhz (see figure 12) may be restored by a 5% increase in the value of the load resis- tor in the passive loading scheme shown in figure 24, or by inserting a trim potentiometer of 100 w in series with the feed- back resistor in the scheme shown in figure 21. the intercept nc r la 100v 0.1% 4.7mf r lb 100v 0.1% 4.7mf output a output b nc 15 13 14 16 19 18 17 11 12 20 6 8 7 5 3 4 10 9 1 2 sig +in atn out ckt com rg1 rg0 rg2 log out log com +v s sig +out sig Cin atn lo atn com bl1 bl2itc Cv s sig Cout 1kv 1kv atn com atn in ad640 nc 4.7v 10v +5v C5v optional termination resistor signal input denotes a short, direct connection to the ground plane. all unmarked capacitors are 0.1mf ceramic (see text) optional offset balance resistor nc = no connect figure 24. connections for a single ad640 to verify basic performance
ad640 rev. d C12C can be adjusted by adding or subtracting a small current to the output. since the slope current is 1 ma/decade, a 50 m a incre- ment will move the intercept by 1 db. note that any error in this current will invalidate the calibration of the ad640. for example, if one of the 5 v supplies were used with a resistor to generate the current to reposition the intercept by 20 db, a 10% variation in this supply will cause a 2 db error in the absolute calibration. of course, slope calibration is unaffected. source resistance and input offset the bias currents at the signal inputs (pins 1 and 20) are typi- cally 7 m a. these flow in the source resistances and generate input offset voltages which may limit the dynamic range because the ad640 is direct coupled and an offset is indistinguishable from a signal. it is good practice to keep the source resistances as low as possible and to equalize the resistance seen at each input. for example, if the source resistance to pin 20 is 100 w , a compensating resistor of 100 w should be placed in series with pin l. the residual offset is then due to the bias current offset, which is typically under 1 m a, causing an extra offset uncertainty of 100 m v in this example. for a single ad640 this will rarely be troublesome, but in some applications it may need to be nulled out, along with the internal voltage offset component. this may be achieved by adding an adjustable voltage of up to 250 m v at the unused input. (pins l and 20 may be interchanged with no change in function.) in most applications there will be no need to use any offset adjustment. however, a general offset trimming circuit is shown in figure 25. r s is the source resistance of the signal. note: 50 w rf sources may include a blocking capacitor and have no dc path to ground, or may be transformer coupled and have a near zero resis- tance to ground. determine whether the source resistance is zero, 25 w or 50 w (with the generator terminated in 50 w ) to find the correct value of bias compensating resistor, r b , which should optimally be equal to r s , unless r s = 0, in which case use r b = 5 w . the value of r os should be set to 20,000 r b to provide a 250 m v trim range. to null the offset, set the source voltage to zero and use a dvm to observe the logarithmic out- put voltage. recall that the log out current of the ad640 exhibits an absolute value response to the input voltage, so the offset potentiometer is adjusted to the point where the logarithmic output turns around (reaches a local maximum or minimum). C5v (source resistance of terminated generator) r b 19 20 12 ad640 r os r s +5v 20kv figure 25. optional input offset voltage nulling circuit; see text for component values at high frequencies it may be desirable to insert a coupling capacitor and use a choke between pin 20 and ground, when pin 1 should be taken directly to ground. alternatively, trans- former coupling may be used. in these cases, there is no added offset due to bias currents. when using two dc coupled ad640s (overall gain 100,000), it is impractical to maintain a sufficiently low offset voltage using a manual nulling scheme. the section cascaded operation explains how the offset can be automatically nulled to submicrovolt levels by the use of a nega- tive feedback network. using higher supply voltages the ad640 is calibrated using 5 v supplies. scaling is very insensitive to the supply voltages (see dc specifications) and higher supply voltages will not directly cause significant errors. however, the ad640 power dissipation must be kept below 500 mw in the interest of reliability and long-term stabil- ity. when using well regulated supply voltages above 6 v, the decoupling resistors shown in the application schematics can be increased to maintain 5 v at the ic. the resistor values are calculated using the specified maximum of 15 ma current into the +v s terminal (pin 12) and a maximum of 60 ma into the Cv s terminal (pin 7). for example, when using 9 v supplies, a resistor of (9 vC5 v)/15 ma, about 261 w , should be included in the +v s lead to each ad640, and (9 vC5 v)/60 ma, about 64.9 w , in each Cv s lead. of course, asymmetric supplies may be dealt with in a similar way. using the attenuator in applications where the signal amplitude is sufficient, the on- chip attenuator should be used because it provides a tempera- ture independent dynamic range (compare figures 18 and 19). figure 26 shows this attenuator in more detail. r1 is a thin-film resistor of nominally 270 w and low temperature coefficient (tc). it is trimmed to calibrate the intercept to 10 mv dc (or C24 dbm for sinusoidal inputs), that is, to an attenuation of nominally 20 dbs at 27 c. r2 has a nominal value of 30 w and has a high positive tc, such that the overall attenuation factor is 0.33%/ c at 27 c. this results in a transmission factor that is proportional to absolute temperature, or ptat. (see intercept stabilization for further explanation.) to improve the accuracy of the attenuator, the atn com nodes are bonded to both pin 3 and pin 4. these should be connected directly to the sig- nal low of the source (for example, to the grounded side of the signal connector, as shown in figure 32) not to an arbitrary point on the ground plane. 432 15 17181920 16 atn com sig Cin sig +in atn com atn lo atn in r3 r4 r1 r2 atn out first amplifier input ad640 figure 26. details of the input attenuator r4 is identical to r2, and in shunt with r3 (270 w thin film) forms a 27 w resistor with the same tc as the output resistance of the attenuator. by connecting pin 1 to atn low (pin 2) this resistance minimizes the offset caused by bias currents. the offset nulling scheme shown in figure 25 may still be used, with the external resistor r b omitted and r os = 500 k w . offset sta- bility is improved because the compensating voltage introduced at pin 20 is now ptat. drifts of under 1 m v/ c (referred to pins 1 and 20) can be maintained using the attenuator.
ad640 rev. d C13C it may occasionally be desirable to attenuate the signal even further. for example, the source may have a full-scale value of 10 v, and since the basic range of the ad640 extends only to 200 mv dc, an attenuation factor of 50 might be chosen. this may be achieved either by using an independent external attenuator or more simply by adding a resistor in series with atn in (pin 5). in the latter case the resistor must be trimmed to calibrate the intercept, since the input resistance at pin 5 is not guaranteed. a fixed resistor of 1 k w in series with a 500 w variable resistor calibrate to an intercept of 50 mv (or C26 dbv) for dc or square wave inputs and provide a 10 v input range. the intercept stability will be degraded to about 0.003 db/ c. operation of cascaded ad640s frequently, the dynamic range of the input will be 50 db or more. ad640s can be cascaded, as shown in figure 27. the balanced signal output from u1 becomes the input to u2. re- sistors are included in series with each log out pin and capacitors c1 and c2 are placed directly between pins 13 and 14 to provide a local path for the rf current at these output pairs. c1 through c3 are chosen to provide the required low-pass corner in conjunction with the load r l . board layout and grounding disciplines are critically important at the high gain (x100,000) and bandwidth (~150 mhz) of this system. the intercept voltage is calculated as follows. first, note that if its log out is disconnected, u1 simply inserts 50 db of gain ahead of u2. this would lower the intercept by 50 db, to C110 dbv for square wave calibration. with the log out of u1 added in, there is a finite zero signal current which slightly shifts the intercept. with the intercept temperature compensa- tion on u1 disabled this zero signal output is C270 m a (see dc specifications) equivalent to a 5.4 db upward shift in the intercept, since the slope is 50 m a/db. thus, the intercept is at C104.6 dbv (C88.6 dbm for 50 w sine calibration). itc may be disabled by grounding pin 8 of either u1 or u2. cascaded ad640s can be used in dc applications, but input offset voltage will limit the dynamic range. the dc intercept is 6 m v. the offset should not be confused with the intercept, which is found by extrapolating the transfer function from its central log linear region. this can be understood by referring to equation (1) and noting that an input offset is simply additive to the value of v in in the numerator of the logarithmic argument; it does not affect the denominator (or intercept) v x . in dc coupled applica- tions of wide dynamic range, special precautions must be taken to null the input offset and minimize drift due to input bias offset. it is recommended that the input attenuator be used, providing a practical input range of C74 dbv ( 200 m v dc) to +6 dbv ( 2 v dc) when nulled using the adjustment circuit shown in figure 25. eliminating the effect of first stage offset usually, the input signal will be sinusoidal and u1 and u2 can be ac coupled. figure 28a shows a low resistance choke at the input of u2 which shorts the dc output of u1 while preserving the hf response. coupling capacitors may be inserted (fig- ure 28b) in which case two chokes are used to provide bias paths for u2. these chokes must exhibit high impedance over the operating frequency range. 20 1 u2 u1 11 10 20 1 u2 u1 11 10 a. b. figure 28. two methods for ac-coupling ad640s alternatively, the input offset can be nulled by a negative feed- back network from the sig out nodes of u2 to the sig in nodes of u1, as shown in figure 29. the low-pass response of the feedback path transforms to a closed-loop high-pass re- sponse. the high gain ( 100,000) of the signal path results in a commensurate reduction in the effective time constant of this network. for example, to achieve a high-pass corner of 100 khz, the low-pass corner must be at 1 hz. in fact, it is somewhat more complicated than this. when the ac input sufficiently exceeds that of the offset, the feedback be- comes ineffective and the response becomes essentially dc coupled. even for quite modest inputs the last stage will be limiting and the output (pins 10 and 11) of u2 will be a square wave of about 180 mv amplitude, dwelling approximately equal times at its two limit values, and thus having a net average value near zero. only when the input is very small does the high- pass behavior of this nulling loop become apparent. consequently, the low-pass time constant can usually be reduced considerably without serious performance degradation. the resistor values are chosen such that the dc feedback is ade- quate to null the worst case input offset, say, 500 m v. there r l = 50v c3 1ma/decade 15 13 14 16 19 18 17 11 12 20 6 8 7 5 3 4 10 9 1 2 sig +in atn out ckt com rg1 rg0 rg2 log out log com +v s sig +out sig Cin atn lo atn com bl1 bl2itc Cv s sig Cout 1kv 1kv atn com atn in u1 ad640 nc 4.7v +5v C5v r1 r2 nc nc 15 13 14 16 19 18 17 11 12 20 6 8 7 5 3 4 10 9 1 2 sig +in atn out ckt com rg1 rg0 rg2 log out log com +v s sig +out sig Cin atn lo atn com bl1 bl2itc Cv s sig Cout 1kv 1kv atn com atn in u2 ad640 c1 10v 10v c2 10v 10v output C50mv/decade 4.7v denotes a connection to the ground plane; observe common connections where shown. all unmarked capacitors are 0.1 mf ceramic. see text for values of numbered components. signal input nc = no connect figure 27. basic connections for cascaded ad640s
ad640 rev. d C14C 15 13 14 16 19 18 17 11 12 20 6 8 7 5 3 4 10 9 1 2 sig +in atn out ckt com rg1 rg0 rg2 log out log com +v s sig +out sig Cin atn lo atn com bl1 bl2itc Cv s sig Cout 1kv 1kv atn com atn in u1 ad640 nc r1 r2 nc nc 15 13 14 16 19 18 17 11 12 20 6 8 7 5 3 4 10 9 1 2 sig +in atn out ckt com rg1 rg0 rg2 log out log com +v s sig +out sig Cin atn lo atn com bl1 bl2itc Cv s sig Cout 1kv 1kv atn com atn in u2 ad640 c1 47pf r3 100v 68v c2 47pf r4 100v 18v l1 (see text) 18v C6v +6v 68v C6v 4.7v u3 ad844 log output +50mv/db (lo) +6v 4.7v denotes a connection to the ground plane; observe common connections where shown. all unmarked capacitors are 0.1 mf ceramic. see text for values of numbered components. signal input r13 1.13kv (see text) nc = no connect figure 30. complete 70 db dynamic range converter for 50 mhzC150 mhz operation must be some resistance at pins 1 and 20 across which the offset compensation voltage is developed. the values shown in the figure assume that we wish to terminate a 50 w source at pin 20. the 50 w resistor at pin 1 is essential, both to minimize offsets due to bias current mismatch and because the outputs at pins 10 and 11 can only swing negatively (from ground to C180 mv) whereas we need to cater for input offsets of either polarity. for a sine input of 1 m v amplitude (C120 dbv) and in the absence of offset, the differential voltage at pins 10 and 11 of u2 would be almost sinusoidal but 100,000 times larger, or 100 mv. the last limiter in u2 would be entering saturation. a 1 m v input offset added to this signal would put the last limiter well into saturation, and its output would then have a different average value, which is extracted by the low-pass network and delivered back to the input. for larger signals, the output ap- proaches a square wave for zero input offset and becomes rect- angular when offset is present. the duty cycle modulation of this output now produces the nonzero average value. assume a maximum required differential output of 100 mv (after averag- ing in c1 and c2) as shown in figure 29. r3 through r6 can now be chosen to provide 500 m v of correction range, and with these values the input offset is reduced by a factor of 500. using 4.7 m f capacitors, the time constant of the network is about 1.2 ms, and its corner frequency is at 13.5 hz. the closed loop high-pass corner (for small signals) is, therefore, at 1.35 mhz. bandwidth/dynamic range trade-offs the first stage noise of the ad640 is 2 nv/ ? hz (short circuited input) and the full bandwidth of the cascaded ten stages is about 150 mhz. thus, the noise referred to the input is 24.5 m v rms, or C79 dbm, which would limit the dynamic range to 77 dbs (C79 dbm to C2 dbm). in practice, the source resistances will also generate noise, and the full bandwidth dynamic range will be less than this. a low-pass filter between u1 and u2 can limit the noise band- width and extend the dynamic range. the simplest way to do this is by the addition of a pair of grounded capacitors at the signal outputs of u1 (shown as c1 and c2 in figure 32). the 20 1 11 10 u2 u1 a ve = C140mv input r1 50v r2 50v a ve = C40mv r3 4.99kv r5 4.99kv C200mv C700mv 4ma 14ma 20 1 11 10 c1 c2 r4 4.99kv r6 4.99kv figure 29. feedback offset correction network C3 db frequency of the filter must be above the highest fre quency to be handled by the converter; if not, nonlinearity in the transfer function will occur. this can be seen intuitively by noting that the system would then contract to a single ad640 at very high frequencies (when u2 has very little input). at inter- mediate frequencies, u2 will contribute less to the output than would be the case if there were no interstage attenuation, result- ing in a kink in the transfer function. more complex filtering may be considered. for example, if the signal has a fairly narrow bandwidth, the simple chokes shown in figure 28 might be replaced by one or more parallel tuned circuits. two separate tuned circuits or transformer coupling should be used to eliminate all undesirable hf common mode coupling between u1 and u2. the choice of q for these circuits requires compromise. frequency sensitive nonlinearities can arise at the edges of the band if the q is set too high; if too low, the transmission of the signal from u1 to u2 will be affected even at the center frequency, again resulting in nonlinearity in the conversion response. in calculating the q, note that the resistance from pins 10 and 11 to ground is 75 w . the input resistance at pins 1 and 20 is very high, but the capacitances at these pins must also be factored into the total lcr circuit. practical applications we show here two applications, using cascaded ad640s to achieve a wide dynamic range. as already mentioned, the use of a differential signal path and differential logarithmic outputs
ad640 rev. d C15C diminishes the risk of instability due to poor grounding. never- theless, it must be remembered that at high frequencies even very small lengths of wire, including the leads to capacitors, have significant impedance. the ground plane itself can also generate small but troublesome voltages due to circulating cur- rents in a poor layout. a printed circuit evaluation board is available from analog devices (part number adeb640) to facilitate the prototyping of an application using one or two ad640s, plus various external components. at very low signal levels various effects can cause significant deviation from the ideal response, apart from the inherent non- linearities of the transfer function already discussed. note that any spurious signal presented to the ad640s is demodulated and added to the output. thus, in the absence of thorough shielding, emissions from any radio transmitters or rfi from equipment operating in the locality will cause the output to appear too high. the only cure for this type of error is the use of very care- ful grounding and shielding techniques. 50 mhzC150 mhz converter with 70 db dynamic range figure 30 shows a logarithmic converter using two ad640s which can provide at least 70 db of dynamic range, limited mostly by first stage noise. in this application, an rf choke (l1) prevents the transmission of dc offset from the first to the sec- ond ad640. one or two turns in a ferrite core will generally suffice for operation at frequencies above 30 mhz. for ex- ample, one complete loop of 20 gauge wire through the two holes in a fair-r ite type 2873002302 core provides an inductance of 5 m h, which presents an im pedance of 1.57 k w at 50 mhz. the shunting effect across the 150 w differential impedance at the signal interface is thus fairly slight. the signal source is optionally terminated by r1. to minimize the input offset voltage r2 should be chosen to match the dc resistance of the terminated source. (however, the offset voltage is not a critical consideration in this ac-coupled application.) note that all unused inputs are grounded; this improves the isolation from the outputs back to the inputs. a transimpedance op amp (u3, ad844) converts the summed logarithmic out put currents of u1 and u2 to a ground ref erenced voltage scaled 1 v per decade. the resistor r5 is nominally 1 k w but is increased slightly to compensate for the slope deficit at the operating frequency, which can be determined from figure 12. the inverting input of u3 forms a virtual ground, so that each logarithmic output of u1 and u2 is loaded by 100 w (r3 or r4). these resistors in conjunction with capacitors c1 and c2 form independent low-pass filters with a time constant of about input level C dbm in 50 v 0 C60 C50 C40 C30 C20 C10 0 +1 C1 error C db 4 1 0 C70 low-pass filtered output C v 2 3 figure 31. logarithmic output and nonlinearity for circuit of figure 30, for a sine wave input at f = 80 mhz 5 ns. these capacitors should be connected directly across pins 13 and 14, as shown, to prevent high frequency output currents from circulating in the ground plane. a second 5 ns time con- stant is formed by feedback resistor r5 in conjunction with the transcapacitance of u3. this filtering is adequate for input frequencies of 50 mhz or above; more elaborate filtering can be devised for pulse applications requiring a faster rise time. in applications where only a long term measure of the input is needed, c1 and c2 can 5kv 0.1mf 0.1mf +15v C15v to u3 and u4 15 13 14 16 19 18 17 11 12 20 6 8 7 5 3 4 9 1 2 10 sig +in atn out ckt com rg1 rg0 rg2 log out log com +v s sig +out sig Cin atn lo atn com bl1 bl2itc Cv s sig Cout 1kv 1kv atn com atn in u2 ad640 c6 0.1mf 68v +6v 68v r7 3.3mv 1/2 ad712 denotes a connection to the ground plane; observe common connections where shown. all unmarked capacitors are 0.1 mf ceramic. offset nulling feedback u4a 5kv signal input 15 1314 16 19 18 17 11 12 20 sig +in atn out ckt com rg1 rg0 rg2 log out log com +v s sig +out sig Cin atn lo atn com bl1 bl2itc Cv s sig Cout 1kv 1kv atn com atn in u1 ad640 6 8 7 5 3 49 12 10 c1 (see text) c2 (see text) c7 4.7mf c8 4.7mf 1 2 3 b offset nulling feedback u4b 7 6 5 a 1/2 ad712 1/2 ad712 u3a 1 2 3 nc r2 50kv r3 50kv u3b 1/2 ad712 7 6 5 r4 200kv r5 200kv log output +100mv/db c4 4.7mf r1 49.9v c3 100mf c5 0.1mf a b +15v C15v to u1 and u2 to u3 and u4 9.1v 9.1v +6v C6v 18v C6v 18v nc = no connect r6 3.3mv figure 32. complete 95 db dynamic range converter
ad640 rev. d C16C be increased and u3 can be replaced by a low speed op amp. figure 31 shows typical performance of this converter. 10 hzC100 khz converter with 95 db dynamic range to increase the dynamic range it is necessary to reduce the bandwidth by the inclusion of a low-pass filter at the signal interface between u1 and u2 (figure 32). to provide operation down to low frequencies, dc coupling is used at the interface between ad640s and the input offset is nulled by a feedback circuit. using values of 0.02 m f in the interstage filter formed by capaci- tors c1 and c2, the hf corner occurs at about 100 khz. u3 (ad712) forms a 4-pole 35 hz low-pass filter. this provides operation to signal frequencies below 20 hz. the filter response is not critical, allowing the use of an electrolytic capacitor to form one of the poles. r1 is restricted to 50 w by the compliance at pin 14, so c3 needs to be large to form a 5 ms time constant. a tantalum capacitor is used (note polarity). the output of u3a is scaled +1 v per decade, and the x2 gain of u3b raises this to +2 v per decade, or +100 mv/db. the differential offset at the output of u2 is low-pass filtered by r6/c7 and r7/c8 and buffered by voltage followers u4a and u4b. the 16s open loop time con stant translates to a closed loop high-pass corner of 10 hz. (this high-pass filter is only operative for very small inputs; see page 13.) figure 33 shows the performance for square wave inputs. since the attenuator is used, the upper end of the dynamic range now extends to +6 dbv and the intercept is at C82 dbv. the noise limited dynamic range is over 100 db, but in practice spurious signals at the input will determine the achievable range. input amplitude at 10khz C1 C90 31.6m log output from circuit of figure 32 C v 0 1 2 3 4 5 6 7 8 9 C80 100m C70 316m C60 1m C50 3.16m C40 10m C30 31.6m C20 100m C10 316m 0 1 10 3.16 dbv v C2 0 2 error from ideal transfer function C db figure 33. logarithmic output and nonlinearity for circuit of figure 32, for a square wave input at f = 10 khz
ad640 rev. d | page 17 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are ro unded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001 070706-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 20 1 10 11 0.100 (2.54) bsc 1.060 (26.92) 1.030 (26.16) 0.980 (24.89) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) fig u re 33. 20-lead plastic dual in-line package [pdip] narrow body (n-20) dimensions shown in inches and (millimeters) compliant to jedec standards mo-047-aa controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.020 (0.50) r bottom view (pins up) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) min 0.120 (3.04) 0.090 (2.29) 3 4 19 18 8 9 14 13 top view (pins down) 0.395 (10.03) 0.385 (9.78) sq 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.22 ) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.020 (0.51) r 0.050 (1.27) bsc 0.180 (4.57) 0.165 (4.19) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier fig u re 34. 20-lead plastic leaded chip carrier [plcc] (p-20) dimensions shown in inches and (millimeters)
ad640 rev. d | page 18 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 20 1 10 11 0.300 (7.62) 0.280 (7.11) pin 1 0.080 (2.03) ma x 0.005 (0.13) min seating plane 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) max 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.100 (2.54) bsc 0.150 (3.81) min 0.320 (8.13) 0.300 (7.62) 0.015 (0.38) 0.008 (0.20) 1.060 (28.92) 0.990 (25.15) figure 35. 20-l e ad side-brazed cera mic dual in-line package [sbdip] (d-20) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are ro unded-off inch equivalents for reference only and are not appropriate for use in design. 1 20 4 9 8 13 19 14 3 18 bottom view 0.028 (0.71) 0.022 (0.56) 45 typ 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) ref 0.200 (5.08) ref 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) 0.342 (8.69) sq 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) 022106-a figur e 36. 20-terminal cerami c leadless chip carrier [lcc] (e-20-1) dimensions shown in inches and (millimeters) ordering guide model 1 temperature range package description package option ad640jnz 0c to 70c 20-lead pdip n-20 ad640jpz 0c to 70c 20-lead plcc p-20 ad640jpz-reel7 0c to 70c 20-lead plcc, 7 tape and reel p-20 ad640be ?40c to +85c 20-terminal lcc e-20-1 AD640BPZ ?40c to +85c 20-lead plcc p-20 ad640td/883b ?55c to +125c 20-lead sbdip d-20 ad640te/883b ?55c to +125c 20-terminal lcc e-20-1 5962-9095502mra ?55c to +125c 20-lead sbdip d-20 5962-9095502m2a ?55c to +125c 20-terminal lcc e-20-1 ad640tchips ?55c to +125c die 1 z = rohs compliant part. revision history 7 /2016rev. c to rev. d changes to specifications section .................................................. 2 updated outline dimensions ....................................................... 17 changes to ordering guide ......................................................... 18 moved outline dimensions .......................................................... 17 moved ordering guide ................................................................. 18
ad640 ?1999C2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d14166-0-7/16 rev. d | page 19

▲Up To Search▲

Price & Availability of AD640BPZ

	To Download AD640BPZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .